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W49L401(t) 256k 16 cmos flash memor y publication release date: august 1 6 , 2002 - 1 - revision a 4 1. general descripti on the W49L401(t) is a 4 - megabit, 3.3 - volt only cmos flash memory organized as 256k 16 bits. the device can be programmed and erased in - system with a standard 3.3 - volt power supply. a 12 - volt v pp is not required. the unique cell archi tecture of the W49L401(t) results in fast program/erase operations with extremely low current consumption (compared to other comparable 3.3 - volt flash memory products). the device can also be programmed and erased using standard eprom programmers. 2. feat ures single voltage operations: - 3.0 - 3.6v read/erase/program fast program operation: - word - by - word programming : 30 m s (typ.) fast erase operation: - page/block erase time: 50 ms (typ.) - chip erase time: 200 ms (typ.) fast read access time: 70 ns endurance: 10k cycles (typ.) twenty - year data retention hardware data protection block configuration - one 8k - word boot block with lockout protection - two 4k - word parameter blocks - one 16k - word main memory array block - seven 32k - word main memory array blocks - 128 uniform 2 k - word pages optional uniform page configuration low power consumption - active current: 10 ma (typ.) - standby current: 5 m a (typ.) automatic program and erase timing with internal v pp generation end of program or erase detection - toggle bit - data polling ry/#by open - drain output provides hardware end - of - write detection hardware #reset pin latched address and data ttl compatible i/ o jedec standard word - wide pinouts available packages: 44 - pin sop, 48 - pin tsop
W49L401(t) - 2 - 3. pin configuration s 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 dq15 a9 a10 a11 a12 a13 a14 a15 #oe 48-pin tsop 24 23 a16 #we #ce a7 a6 a5 a4 a3 a2 a1 a0 21 22 48 47 46 45 44 43 42 41 nc #reset nc nc a8 dq11 dq3 dq10 dq2 dq9 dq1 dq8 dq0 v dd dq7 dq14 dq6 dq13 dq5 dq12 dq4 nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 dq15 #oe 44-pin sop 24 23 a16 #ce a0 21 22 40 39 38 37 36 35 34 33 32 31 30 29 28 27 44 43 42 41 a7 a6 a5 a4 a3 a2 a1 a9 a10 a11 a12 a13 a14 a15 #we #reset a8 dq11 dq3 dq10 dq2 dq9 dq1 dq8 dq0 v dd dq7 dq14 dq6 dq13 dq5 dq12 dq4 nc 26 25 v ss v ss v ss v ss a17 a17 nc ry/#by ry/#by nc nc 4. block diagram control output buffer d e c o d e r #ce #oe #we a0 . . a17 . . dq0 dq15 #reset boot block 8k words parameter block2 4k words parameter block1 4k words 3ffff 04000 03fff 03000 02fff 02000 01fff 00000 W49L401 main memory 240k words boot block 8k words parameter block2 4k words parameter block1 4k words 3ffff 3e000 3dfff 3d000 3cfff 3c000 3bfff 00000 W49L401t ry/#by (1x16k words 7x32k words) main memory 240k words (1x16k words 7x32k words) 5. pin desc ription symbol pin name #reset reset ry/#by ready/#busy output a0 - a17 address inputs dq0 - dq15 data inputs/outputs #ce chip enable #oe output enable #we write enable v dd power supply v ss ground nc no connection
w49l4 01(t) publication release date: august 1 6 , 2002 - 3 - revision a 4 6. functional descri ptio n read mode the read operation of the W49L401(t) is controlled by #ce and #oe, both of which have to be low for the host to obtain data from the outputs. #ce is used for device selection. when #ce is high, the chip is de - selected and only standby power wil l be consumed. #oe is the output control and is used to gate data to the output pins. the data bus is in high impedance state when either #ce or #oe is high. refer to the timing waveforms for further details. reset operation the #reset input pin can be use d in some application. when #reset pin is at high state, the device is in normal operation mode. when #reset pin is driven low for at least a period of t rp , it will halt the device and all outputs are at high impedance state. the device also resets the int ernal state machine to read array data. the operation that was interrupted should be reinitiated once the device is ready to accept another command sequence to assure data integrity. as the high state re - asserted to the #reset pin, the device will return t o read or standby mode, it depends on the control signals. the system can read data t rh after the #reset pin returns to v ih . the other function for #reset pin is temporary reset the boot block. by applying the 12v to #reset pin, the boot block can be repro grammed even though the boot block lockout function is enabled. boot block operation there is one 8k - word boot block in this device, which can be used to store boot code. it is located in the first 8k words (for W49L401t, located in the last 8k words) of t he memory with the address range from 0000(hex) to 1fff(hex). (for W49L401t, address range from 3e000h to 3ffffh) see command codes for boot block lockout enable for the specific code. once this feature is set, the data for the designated block cannot be e rased or programmed (programming lockout); the regular programming method can change the data in other memory locations. there is one condition that the lockout feature can be over - ridden. just apply 12v to #reset pin, the lockout feature will temporarily be inactivated and the boot block can be erased/programmed. once the #reset pin returns to cmos/ttl level, the lockout feature will be activated again. in order to detect whether the boot block feature is set on the 8k - words block, users can perform softwa re command sequence: enter the product identification mode (see command codes for identification/boot block lockout detection for specific code), and then read from address "0002 hex". if the output data in dq0 is "1", the boot block programming lockout f eature is activated; if the output data in dq0 is "0", the lockout feature is inactivated and the block can be erased/programmed. to return to normal operation, perform a three - byte command sequence (or an alternate single - word command) to exit the identif ication mode. for the specific code, see command codes for identification/boot block lockout detection. chip erase operation the chip - erase mode can be initiated by a six - word command sequence. after the command loading cycle, the device enters the intern al chip erase mode, which is automatically timed and will be completed in a fast 200 ms (typical). the host system is not required to provide any control or timing during this operation. the entire memory array will be erased to ffff(hex) by the chip erase operation if the boot block programming lockout feature is not activated. once the boot block lockout feature is activated, the chip erase function will erase all the blocks/pages except the boot block.
W49L401(t) - 4 - block/page erase operation the W49L401(t) provides b oth uniform small page (2k - word) and non - symmetrical block (4k/8k/16k/32k - word) erase capabilities for versatile flash applications. each block or page can be erased individually by initiating a six - word command sequence. the block address (ba) or page add ress (pa) is latched on the falling #we edge of the sixth cycle while the xx30/xx50(hex) data input command is latched at the rising edge of #we. after the command loading cycle, the device enters the internal block/page erase mode, which is automatically timed and will be completed in a fast 50 ms (typical). the host system is not required to provide any control or timing during this operation. the device will automatically return to normal read mode after the erase operation completed. data - polling, toggl e - bit and/or ry/#by pin can be used to detect end of erase cycle. the bootblock (8k - words) consists of 4 corresponding uniform pages of 2k - words each. when the boot block lockout feature is activated, any page/block erase command with the associated pa/ba within the bootblock address range (0000 - 01fff for W49L401 , and 3e000 - 3ffff for W49L401t ) will be ignored and the device will return to read mode without any data changes. program operation the W49L401(t) is programmed on a word - by - word basis. program ope ration can only change logical data "1" to logical data "0" the erase operation (changed entire data in individual page/block or whole chip from "0" to "1") is needed before programming. the program operation is initiated by a 4 - word command cycle (see com mand codes for word programming). the device will internally enter the program operation immediately after the word - program command is entered. the internal program timer will automatically time - out (50 m s max. - t bp ) once completed and return to normal read mode. data_polling, toggle_bit and/or ry/#by pin can be used to detect end of program cycle. hardware data protection the integrity of the data stored in the W49L401(t) is also hardware protected in the following ways: (1) noise/g litch protection: a #we pulse of less than 10 ns in duration will not initiate a write cycle. (2) v dd power up/down detection: the programming operation and read are inhibited when v dd is less than 1.8v typical. (3) write inhibit mode: forcing #oe low, #ce high, or #we high will inhibit the write operation. this prevents inadvertent writes during power - up or power - down periods. (4) v dd power - on delay: when v dd has reached its sense level, the device will automatically time - out 10 ms before any write (erase/ program) operation. data polling (dq 7 ) - write status detection the W49L401(t) includes a data polling feature to indicate the end of a program or erase cycle. when the W49L401(t) is in the internal program or erase cycle, any attempt to read dq 7 of the la st word loaded will receive the complement of the true data. once the program or erase cycle is completed, dq 7 will show the true data. note that, dq 7 will show logical "0" during the erase cycle. and it will become logical "1" or true data when the erase cycle is completed. toggle bit (dq 6 ) - write status detection in addition to data polling, the W49L401(t) provides another method for determining the end of a program cycle. during the internal program or erase cycle, any consecutive attempts to read dq 6 wi ll
w49l4 01(t) publication release date: august 1 6 , 2002 - 5 - revision a 4 produce alternating 0's and 1's. when the program or erase cycle is completed, this toggling between 0's and 1's will stop. the device is then ready for the next operation. ready/#busy the W49L401(t) also provides the hardware method to detect the compl etion of program/erase cycle . the ry/#by output pin will be asserted low (busy) during programming/erasing operations, and will be released to high state by an external pull - up (ready) when internal program/erase cycle is completed. this is an open - drain output pin for easy external connection. product identification the product id operation outputs the manufacturer code and device code. programming equipment automatically matches the device with its proper erase and programming algorithms. the manufacture r and device codes can be accessed by software or hardware operation. in the software access mode, a six - word (or jedec 3 - word) command sequence can be used to access the product id. a read from address 0000h outputs the manufacturer code, 00da(hex). a rea d from address 0001(hex) outputs the device code, 003d(hex ) for bottom boot (and tbd for top boot). the product id operation can be terminated by a three - word command sequence or an alternative one - word command sequence (see command definition table). in t he hardware access mode, access to the product id is activated by forcing #ce and #oe low, #we high, and raising a9 to v hh ( 12v + / - 0.5v). table of operating modes operating mode selection (v hh = 12v 0.5v) pins mode #ce #oe #we # reset address dq. read v il v il v ih v ih a in dout erase/program v il v ih v il v ih a in din standby v ih x x v ih x high z v ih x x v ih x high z x v il x v ih x high z/d out erase/program inhibit x x v ih v ih x high z/d out output disable x v ih x v ih x high z a0 = v il ; a1 - a15 = v il ; a9 = v hh manufacturer code 00da (hex) product id v il v il v ih v ih a0 = v ih ; a1 - a15 = v il ; a9 = v hh device code 003d (hex) for bottom tbd for top reset x x x v il x high z
W49L401(t) - 6 - table of software command definition 1st cycle 2nd cycle 3rd cycle 4th cycle 5th cycle 6th cycle command desc ription no. of cycles addr. data addr. data addr. data addr. data addr. data addr. data chip erase 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 5555 10 block erase 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 ba (5) 30 page erase 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 pa (4) 50 word program 4 5555 aa 2aaa 55 5555 a0 a in d in boot block lockout 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 5555 40 product id entry 3 5555 aa 2aaa 55 5555 90 product id exit (1) 3 5555 aa 2aaa 55 5555 f0 product id exit (1) 1 xxxx f0 notes: 1. address format: a14 - a0 (hex); data format: dq15 - dq8 (don't care); dq7 - dq0 (hex) 2. if an y invalid command or read cycle (both #ce & #oe are active low) is inserted during any of the above software command sequence, it will abort the operation and the device return to read mode. 3. either one of the two product id exit commands can be used, an d read mode is resumed after this command executed. 4. pa: page address W49L401 W49L401t pa = 00000h to 007ffh for page0 pa = 3f800h to 3ffffh for page0 pa = 00800h to 00fffh for page1 pa = 3f000h to 3f7ffh for page1 pa = 01000h to 017ffh for page2 pa = 3e800h to 3efffh for page2 pa = 01800h to 01fffh for page3 pa = 3e000h to 3e7ffh for page3 pa = 02000h to 027ffh for page4 pa = 3d800h to 3dfffh for page4 pa = 02800h to 02fffh for page5 pa = 3d000h to 3d7ffh for page5 ? ? ? ? ? ? pa = 3d000h to 3 d7ffh for page122 pa = 02800h to 02fffh for page122 pa = 3d800h to 3dfffh for page123 pa = 02000h to 027ffh for page123 pa = 3e000h to 3e7ffh for page124 pa = 01800h to 01fffh for page123 pa = 3e800h to 3efffh for page125 pa = 01000h to 017ffh for page1 25 pa = 3f000h to 3f7ffh for page126 pa = 00800h to 00fffh for page126 pa = 3f800h to 3ffffh for page127 pa = 00000h to 007ffh for page127 5. ba: block address W49L401 W49L401t ba = 00000h to 01fffh for boot block (8kw) ba = 3e000h to 3ffffh for boot b lock (8kw) ba = 02xxxh for parameter block1 (4kw) ba = 3dxxxh for parameter block1 (4kw) ba = 03xxxh for parameter block2 (4kw) ba = 3cxxxh for parameter block2 (4kw) ba = 04000h to 07fffh for main memory block1 (16kw) ba = 38000h to 3bfffh for main mem ory block1 (16kw) ba = 08000h to 0ffffh for main memory block2 (32kw) ba = 30000h to 37fffh for main memory block2 (32kw) ba = 10000h to 17fffh for main memory block3 (32kw) ba = 28000h to 2ffffh for main memory block2 (32kw) ba = 18000h to 1ffffh for m ain memory block4 (32kw) ba = 20000h to 27fffh for main memory block3 (32kw) ba = 20000h to 27fffh for main memory block5 (32kw) ba = 18000h to 1ffffh for main memory block4 (32kw) ba = 28000h to 2ffffh for main memory block6 (32kw) ba = 10000h to 17fffh for main memory block5 (32kw) ba = 30000h to 37fffh for main memory block7 (32kw) ba = 08000h to 07fffh for main memory block7 (32kw) ba = 38000h to 3ffffh for main memory block8 (32kw) ba = 00000h to 07fffh for main memory block8 (32kw)
w49l4 01(t) publication release date: august 1 6 , 2002 - 7 - revision a 4 embedded prog ramming algorithm start write program command sequence (see below) increment address programming completed #data polling/ toggle bit last address ? no yes 5555h/aah 2aaah/55h 5555h/a0h program address/program data program command sequence (address/command): pause t ec /t sec
W49L401(t) - 8 - embedded erase algorithm start write erase command sequence (see below) erasure completed #data polling or toggle bit successfully completed 5555h/aah 5555h/aah 2aaah/55h 2aaah/55h 5555h/80h 5555h/10h chip erase command sequence (address/command): 5555h/aah 5555h/aah 2aaah/55h 2aaah/55h 5555h/80h block address/30h (address/command): 5555h/aah 5555h/aah 2aaah/55h 2aaah/55h 5555h/80h pageaddress/50h individual pageerase (address/command): individual blockerase command sequence command sequence pause t ec /t sec
w49l4 01(t) publication release date: august 1 6 , 2002 - 9 - revision a 4 embedded #data polling algorithm start read byte (dq0 - dq7) address = va pass dq7 = data ? yes no va = byte address for programming = any of the sector addresses within the sector being erased during sector erase operation = valid address equals any sector group address during chip erase embedded toggle bit algorithm start read byte (dq0 - dq7) address = don't care dq6 = toggle ? yes no pass
W49L401(t) - 10 - product identification entry (1) load data 55 to address 2aaa load data 90 to address 5555 pause 10 s product identification and boot block lockout detection mode (3) read address = 0000 data = 00da read address = 0001 data = 003d for bottom read address = 0002 data in dq0 =1/0 (4) product identification exit(6) load data 55 to address 2aaa load data f0 to address 5555 normal mode (5) (2) (2) load data aa to address 5555 m load data aa to address 5555 pause 10 s m tbd for top software product identification and boot block lockout detecti on acquisition flow
w49l4 01(t) publication release date: august 1 6 , 2002 - 11 - revision a 4 boot block lockout enable acquisition flow boot block lockout feature set flow load data aa to address 5555 load data 55 to address 2aaa load data 80 to address 5555 load data aa to address 5555 load data 55 to address 2aaa load data 40 to address 5555 pause 200 ms exit
w49l4 01(t) - 12 - 7. dc characteristic s absolute maximum ratings parameter rating unit power supply voltage to v ss potential - 0.5 to +4.6 v operating temperature 0 to +70 c storage temperature - 65 to +150 c d.c. voltage on any pin to ground potential except a9 or #reset - 0.5 to v dd +1.0 v transient voltage (<20 ns) on any pin to ground potential - 1.0 to v dd +1.0 v voltag e on a9 or #reset pin to ground potential - 0.5 to 12.5 v note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device. dc operating characteristics (v dd = 3.0 ~ 3.6v, v ss = 0v , t a = 0 to 70 c) limits parameter sym. test conditions min. typ. max. unit v dd current - read i cc #ce = #oe = v il , #we = v ih , all dqs open address inputs = v il /v ih , at f = 5 mhz - 10 20 ma v dd current - write i ccw #ce = #w e = v il , #oe = v ih - 15 25 ma standby v dd current (ttl input) i sb 1 #ce = v ih , all dqs open other inputs = v il /v ih - - 1 ma standby v dd current (cmos input) i sb 2 #ce = v dd - 0.3v, all dqs open other inputs = v dd - 0.3v / v ss - 5 50 m a input leakage current i li v in = v ss to v dd - - 10 m a output leakage current i lo v out = v ss to v dd - - 10 m a input low voltage v il - - 0.2 - 0.8 v input high voltage v ih - 2.0 - v dd +0.3 v output low volt age v ol i ol = 2.1 ma - - 0.45 v output high voltage v oh i oh = - 0.4 ma 2.4 - - v
w49l4 01(t) publication release date: august 1 6 , 2002 - 13 - revision a 4 power - up timing parameter symbol typical unit power - up to read operation t pu . read 200 m s power - up to write operation t pu . write 10 ms capacitance (v dd = 3.3v, t a = 25 c, f = 1 mhz) parameter symbol conditions max. unit i/o pin capacitance c i/o v i/o = 0v 12 pf input capacitance c in v in = 0v 6 pf 8. ac characteristic s ac test conditions parameter conditions input pulse lev els 0v to 0.9 v dd input rise/fall time < 5 ns input/output timing level 1.5v/1.5v output load 1 ttl gate and c l = 30 pf ac test load and waveform +3.3v 1.8k 1.3k d out w w (including jig and scope) input 0v test point test point 1.5v 1.5v output 30 pf 0.9v dd
W49L401(t) - 14 - ac characteristics, continued read cycle timing parameters ( v dd = 3.0 ~ 3.6v , v ss = 0v, t a = 0 to 70 c) 70 ns parameter symbol min. max. unit read cycle time t rc 70 - ns chip enable access time t ce - 70 ns address access time t aa - 70 ns output enable access time t oe - 35 ns #ce low to active output t clz 0 - ns # oe low to active output t olz 0 - ns #ce high to high - z output t chz - 25 ns #oe high to high - z output t ohz - 25 ns output hold from address change t oh 0 - ns note: the parameter of t clz , t olz , t chz , t ohz are characterized only and is not 100% tested. wr ite cycle timing parameters parameter symbol min. typ. max. unit address setup time t as 10 - - ns address hold time t ah 100 - - ns #we and #ce setup time t cs 10 - - ns #we and #ce hold time t ch 10 - - ns #oe high setup time t oes 10 - - ns #oe high ho ld time t oeh 0 - - ns #ce pulse width t cp 100 - - ns #we pulse width t wp 100 - - ns #we high width t wph 50 - - ns data setup time t ds 100 - - ns data hold time t dh 10 - - ns word programming time t bp - 30 50 m s page erase cycl e time t pec - 25 50 ms block erase cycle time t bec - 25 50 ms chip erase cycle time t ec - 100 200 ms note: all ac timing signals observe the following guidelines for determining setup and hold times: (a) high level signal's reference level is v ih a nd (b) low level signal's reference level is v il .
w49l4 01(t) publication release date: august 1 6 , 2002 - 15 - revision a 4 ac characteristics, continued data polling and toggle bit timing parameters 70 ns parameter sym. min. max. unit #oe to data polling output delay t oep - 35 ns #ce to data polling output delay t cep - 7 0 ns #we high to #oe low for data polling t oehp 100 - ns #oe to toggle bit output delay t oet - 35 ns #ce to toggle bit output delay t cet - 70 ns #we high to #oe low for toggle bit t oeht 100 - ns hardware reset timing parameters parameter sym. min. max . unit #reset pulse width t rp 500 - ns #reset high time before read (1) t rh 50 - m s note: 1. the parameters are characterized only and is not 100% tested.
W49L401(t) - 16 - 9. timing waveforms read cycle timing diagram address a17-0 dq15-0 data valid data valid high-z #ce #oe #we t rc v ih t clz t olz t oe t ce t oh t aa t chz t ohz high-z #we controlled co mmand write cycle timing diagram address a17-0 dq15-0 data valid #ce #oe #we t as t cs t oes t ah t ch t oeh t wph t wp t ds t dh
w49l4 01(t) publication release date: august 1 6 , 2002 - 17 - revision a 4 timing waveforms, continued #ce controlled command write cycle timing diagram high z data valid #ce #oe #we dq15-0 t as t ah t cph t oeh t dh t ds t cp t oes address a17-0 program cycle timing diagram address a17-0 word 0 word 1 word 2 internal write start dq15-0 #ce #oe #we word program cycle t bp t wph t wp 5555 5555 2aaa xxaa xxa0 xx55 address data-in word 3 * * *note: it is not allowed to assert read operation(#ce & #oe are both active) during the command sequence. if read command is asserted during the command sequence, then the device will return to read mode (abort write).
W49L401(t) - 18 - timing waveforms, contin ued #data polling timing diagram address a17-0 dq7 #we #oe #ce x x x x t oehp t cep t oep an an an an t ec, t bp, t bec or t pec toggle bit timing diagram address a17-0 dq6 #ce #oe #we t oeht t cet t oet t ec, t bp, t bec or t pec
w49l4 01(t) publication release date: august 1 6 , 2002 - 19 - revision a 4 timing waveforms, continued boot block lockout enable timing diagram sw23 sw1 sw0 address a17-0 dq15-0 #ce #oe #we sw3 sw4 sw5 six-word code for boot block lockout feature enable t wp t wph 5555 2aaa 5555 5555 2aaa 5555 xxaa xx55 xx80 xxaa xx55 xx40 *note: it is not allowed to assert read operation(#ce & #oe are both active) during the command sequence. if read command is asserted during the command sequence, then the device will return to read mode(abort write). 200us chip erase timing diagr am sw2 sw1 sw0 address a17-0 dq15-0 #ce #oe #we sw3 sw4 sw5 internal erase starts six-word code for 3.3v-only software chip erase t wp t wph t ec 5555 2aaa 5555 5555 2aaa 5555 xxaa xx55 xx80 xxaa xx55 xx10
W49L401(t) - 20 - timing waveforms, continued block/page erase timing diagram sw2 sw1 sw0 address a17-0 dq15-0 #ce #oe #we sw3 sw4 sw5 internal erase starts six-word code for 3.3v-only software block/page erase t wp t wph t bec or xx555 xx2aa xx555 xx555 xx2aa ba xxaa xx55 xx80 xxaa xx55 xx30 ba = block address; pa = page address *note: it is not allowed to assert read operation(#ce & #oe are both active) during the command sequence. if read command is asserted during the command sequence, then the device will return to read mode(abort write). t pec pa xx50 ready/#busy timing diagram address a17-0 dq15-dq0 #we #oe #ce pd invalid x x t cep t oehp t oep t oes an an an an ry/#by tbusy trb program/erase in progress
w49l4 01(t) publication release date: august 1 6 , 2002 - 21 - revision a 4 timing waveforms, continued reset timing diagram #ce #oe #reset t rh t rp
W49L401(t) - 22 - 10. ordering informa tion part no. access time ( n s) operating voltage (v) boot block location package W49L401s - 70b 70 3.0 ~ 3.6 bottom 44 - pin sop W49L401t - 70b 70 3.0 ~ 3.6 bottom 48 - pin tsop (12 mm 20 mm) W49L401ts70b 70 3.0 ~ 3 .6 top 44 - pin sop W49L401tt70b 70 3.0 ~ 3.6 top 48 - pin tsop (12 mm 20 mm) notes: 1. winbond reserves the right to make changes to its products without prior notice. 2. purchasers are responsible for performing appropriate quality assurance testing on p roducts intended for use in applications where personal injury might occur as a consequence of product failure. 11. how to read the top marking example: the top marking of 48 - pin tsop W49L401t - 70b 1 st line: winbond logo 2 nd line: the part number: W49L401t - 70b 3 rd line: the lot number 4 th line: the tracking code: 149 o b aa 149: packages made in ?01, week 49 o: assembly house id: a means ase, o means ose, ... etc. b: ic revision; a means version a, b means version b, ... etc. aa: process code W49L401t - 70b 2138977a - a12 149o baa
w49l4 01(t) publication release date: august 1 6 , 2002 - 23 - revision a 4 12. package dimensions 48 - pin tsop (12 mm 20 mm) e 1 48 b e d y a1 a a2 l1 l c h d 0.020 0.004 0.007 0.037 0.002 min. 0.60 y l l1 c 0.50 0.10 0.70 0.21 dimension in mm a a2 b a1 0.95 0.17 0.05 symbol min. 1.20 0.27 1.05 1.00 0.22 max. nom. 0.028 0.008 0.024 0.011 0.041 0.047 0.009 0.039 nom. dimension in inches max. e h d 0 5 0 5 e d 18.3 18.4 18.5 19.8 20.0 20.2 11.9 12.0 12.1 0.720 0.724 0.728 0.780 0.787 0.795 0.468 0.472 0.476 0.10 0.80 0.031 0.004 0.020 0.50 q q 44 - pin sop e b l d c a2 seating plane y a1 a e 1 22 23 44 h e l1 q 0 0.089 0.004 0.516 0.622 16.00 h 0 15.80 7 16.20 13.30 b e d c 28.07 13.10 a1 a2 a 2.26 13.50 28.32 28.19 3.00 2.82 7 0.638 0.630 0.111 0.118 0.531 1.105 1.115 1.110 0.524 min. dimension in inches symbol dimension in mm min. nom. max. max. nom. 0.10 e l l1 y q 0.014 0.020 0.016 0.004 0.008 0.006 0.024 0.040 0.032 0.053 0.004 0.36 0.50 0.41 0.10 0.21 0.15 1.12 1.42 1.27 0.044 0.056 0.050 0.60 1.00 0.80 1.35 0.10 e
W49L401(t) - 24 - 13. version history version date page description a1 ap r. 2001 - initial issued a2 july 2001 18 change t rh from 50 ns to 10 m s a 3 january 2, 2002 1, 3, 6, 15 delete the description of auto - power saving 18 change t rh from 10 m s to 30 m s ( min.) change t ec from 200/1000 to 100/200 ms (typ./max.) 17 ch ange t pec, t pbc from 50/200 to 25/50 ms (typ./max.) 1, 18, 19, 26 delete read access time of 55 ns 26 add how to read the top marking 9, 10, 11, 12, 13 delete old flow chart and add embedded algorithm 4 modify v dd power up/down detection in har dware data protection 21 modify program cycle timing diagram a 4 august 1 6 , 2002 9 - 13 modify flow charts 23 modify reset timing diagram headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5665577 http://www.winbond.com.tw/ taipei office tel: 886-2-8177-7168 fax: 886-2-8751-3579 winbond electronics corporation america 2727 north first street, san jose, ca 95134, u.s.a. tel: 1-408-9436666 fax: 1-408-5441798 winbond electronics (h.k.) ltd. no. 378 kwun tong rd., kowloon, hong kong fax: 852-27552064 unit 9-15, 22f, millennium city, tel: 852-27513100 please note that all data and specifications are subject to change without notice. all the trade marks of products and companies mentioned in this data sheet belong to their respective owners. winbond electronics (shanghai) ltd. 200336 china fax: 86-21-62365998 27f, 2299 yan an w. rd. shanghai, tel: 86-21-62365999 winbond electronics corporation japan shinyokohama kohoku-ku, yokohama, 222-0033 fax: 81-45-4781800 7f daini-ueno bldg, 3-7-18 tel: 81-45-4781881 9f, no.480, rueiguang rd., neihu chiu, taipei, 114, taiwan, r.o.c.

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